The present invention relates in general to data processing. In some aspects, the present invention relates to decreasing effective data access latency by varying the timing of error detection processing in a memory subsystem of a data processing system. In other aspects, the present invention relates to improving utilizing of processing resources by speculatively finishing instructions associated with high latency operations.
In processor chip design, the trend has been to include an ever increasing number of processor cores per processor chip. Increasing the number of processor cores increases the volume of data consumed by execution of the processor cores, and accordingly places pressure on the bit rates of chip-to-chip interconnects and external memory (e.g., dynamic random access memory (DRAM)) to supply the required volume of data. However, these higher bit rates result in higher inherent bit error rates on the interconnects, thus requiring more robust error-correcting code (ECC) and/or cyclic redundancy check (CRC) codes to ensure a reasonable level of data integrity. Further, complex error codes, such as ECC and CRC, tend to increase access latency due to the need for deeper error correction logic pipelines for error detection and correction.
Another trend impacting processor chip design is that DRAM access latency, while continuing to slowly improve over recent years, has not kept pace with increases in processor core clock rates. Thus, external memory access latency, as measured relative to processor clock rates, has actually degraded. The conventional technique for compensating for external memory access latency has been to implement larger and deeper on-chip cache hierarchies to buffer frequently used data closer to the consuming processor cores. However, limits in overall chip sizes forces a tradeoff between the number of processor cores and the amount of cache memory on the chip. Consequently, the opportunity to improve effective memory access latency simply by increasing on-chip cache capacity is limited.